1. Field of the Invention
The present invention generally relates to clock signals used for timing and synchronization of digital data processing devices and systems and, more particularly, to clock signal duty-cycle correction.
2. Background Description
As many clock driven digital systems are required to perform at higher and higher speeds, designers are investigating different options to achieve this high speed operation. Designers may decide to use both the rising and the falling edge of a given clock signal to double the total number of operations. However, this requires a clock to output accurate 50% duty-cycle to prevent or reduce jitters and other timing related aberrations.
At relatively low frequencies of clock signals, one method to provide a desired symmetrical clock signal uses a conventional flip-flop circuit to perform an equivalent division-by-two for deriving an output clock signal frequency. The source clock frequency must be two times faster than the desired circuit design operating frequency for this method. However, as frequencies increase, the source clock frequency will reach the technology limitation before reaching the circuit design operating frequency. Conventional methods or topologies that have been proposed do not generate a very accurate multiply-by-2 output frequency because some of these methods use a digital controller to select a fixed number of delays. In the case of varying duty-cycles, using a fixed number of delays is not effective to generate accurate multiply-by-2 output frequencies.
It is therefore an object of the present invention to provide a duty-cycle correction circuit capable of correcting a clock with arbitrary duty-cycle to a 50% duty-cycle clock, with its original frequency maintained. Another object of the invention is to provide a method of translating a non-50% duty-cycle clock to an accurate 50% duty-cycle clock. Another, more particular object of the invention is to provide a duty-cycle correction circuit for correcting a clock with arbitrary duty-cycle to a 50% duty-cycle clock that is simple and cost efficient.
According to the invention, the duty-cycle correction circuit includes a divide-by-2 frequency divider and a multiply-by-2 clock doubler connected to the frequency divider. The present invention utilizes negative feedback, a reference 50% duty-cycle clock signal, and a current controlled delay block to maintain an accurate multiply-by-2 output frequency with 50% duty-cycle. A non-50% duty-cycle input clock signal is translated to an accurate 50% duty-cycle clock signal by converting a non-50% duty-cycle input clock signal having an input frequency to a 50% duty-cycle reference signal having a frequency of half the input frequency. The frequency of the 50% duty-cycle reference source signal is then converted to the input frequency while using an analog negative feedback to maintain a 50% duty-cycle.
In a preferred embodiment, the duty-cycle correction circuit translates the non50% duty-cycle clock signal to an accurate 50% duty-cycle clock using the divide-by-2 frequency divider and multiply-by-2 clock doubler. The divide-by-2 frequency divider converts the non-50% duty cycle input clock signal to the 50% duty-cycle reference signal having half of the original frequency. Then, the multiply-by-2 clock doubler converts this 50% duty-cycle reference signal back to the frequency of the inputted clock signal while using an analog negative feedback to maintain an accurate 50% duty-cycle. In this case, the source clock frequency and the design operating frequency are identical and can be pushed towards the technology limit.